In supervisor mode, instruction addresses correspond directly to physical memory.
2.
Memory barrier instructions address reordering effects only at the hardware level.
3.
When that occurs ( the STL's next instruction address remains 0003 ) execution continues as follows:
4.
To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction.
5.
The effective address for a PC-relative instruction address is the offset parameter added to the address of the next instruction.
6.
Later machines would use more complicated and accurate algorithms ( branch prediction and branch target prediction ) to guess the next instruction address.
7.
This was achieved by using map tables held in fast parity checked RAM which mapped one byte opcodes onto micro-instruction addresses.
8.
Maximum memory is limited by the length of the instruction address field of 17 bits, or 128K Words ( 512K Bytes ).
9.
Also, a Harvard architecture machine has distinct code and data address spaces : instruction address zero is not the same as data address zero.
10.
Note that when the flash size is over 64K words ( 128 KBytes ), instruction addresses can no longer be encoded in just two bytes.
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